Method for the coding/decoding of vliw cached instructions

ABSTRACT

A method for controlling functional units in a processor is provided. During a configuration phase of the processor, a series of primary instruction words from the translation of a programme code are subjected to a division into series of instruction word bits. By this, the instruction words controlling the processor during a programme execution are generated with a full instruction word size and buffered in an instruction word memory (cache). The method improves the processor performance in the execution phase by increasing the degree of compression of the primary instruction words into divided instruction word bits. This is acheived independent of special features such as periodicity of the Function Instruction Word bit. First during the configuration phase, a division of a primary instruction word into a Tagged Very Long Instruction Word occurs. Next, this Tagged Very Long Instruction Word is transformed into a Headed Very Long Instruction Word, which includes a general header. The transformed Word has a code-compressed structure and replaces all functions of the Tagged Very Long Instruction Word.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of International Patent ApplicationNo. PCT/DE03/01748 filed Dec. 5, 2003, which claims priority to GermanPatent Application No. DE20021025099 filed Jun. 5, 2002, both of whichapplications are hereby incorporated by reference herein in theirentireties.

FIELD OF THE INVENTION

The invention relates to the structure and operation of a processor. Inparticular, the invention relates to a method for actuating functionunits in a processor.

BACKGROUND OF THE INVENTION

In some processors, a configuration phase involves a series of primaryinstruction words that comes from a translation of a program code beingdivided into a series of instruction word parts, and a program cyclewhich actuates the processor subsequently involving instruction wordsthat are generated in the full instruction word length as a VLIW (VeryLong Instruction Word) and are buffer-stored in an instruction wordmemory (cache).

To this end, various solutions are known which deal with a respectiveadvantageous variant for the synthesis of a VLIW (very Long InstructionWord) from the instruction words which arise during the program cycle.

A common feature of these solutions is that the primary instructionwords resulting from a translation of the program code are generated asa series of divided instruction word parts.

A current VLIW is thus constructed from a limited number of functioninstruction words (FIW), each of these FIWs actuating precisely onefunction unit (FU) in the processor.

German patent specification DE 198 59 389 C1 characterizes the prior artfor methods of the type mentioned at the outset.

In the case of this solution, the primary instruction words which arepresent in the program are divided into individual program words, whichare also advantageously referred to as TVLIW (Tagged Very LongInstruction Word) containers.

They are called TVLIW containers because the individual program word ismade up not only of an information part, which is represented primarilyby an FIW (Function Instruction Word), but also the details regardingthe write and read row numbers of an instruction word memory which is tobe used. The latter details represent a tag for the FIW.

In addition, the program word also includes the details regarding how tohandle the respective content of the instruction word memorycharacterized in this manner, and these are thus represented by anoperating code (Opcode).

In the case of the aforementioned method, the data length of the programto be processed in the processor is advantageously reduced in order tokeep down the hardware complexity and hence the costs for implementingthe respective processor.

In addition, various solutions are known which with a respectiveadvantageous variant for synthesis of a VLIW (Very Long InstructionWord) the FIWs which arise during the program cycle.

Hence, the printed document 102 03 541.5 for the German patentapplication outlines the continuing prior art.

In the case of this prior art, the division of the primary instructionwords which is carried out in a configuration phase is expanded by asubsequent methodological automatic similarity analysis, the result ofwhich is that the instruction word parts which have been selected withparticular similarity features (periodic property) and hence can be usedrepeatedly are combined.

This series of instruction word parts is used in the subsequentprocessing phase to produce the VLIW with an operating code which iscommon in this regard and a flag (which is valid for all members of theseries) for its periodic property which has the number of members addedto it.

In this way, this specific compression operation involves theperformance, in the configuration phase, of the selection and flaggingof the instruction word parts which are provided for buffer-storage inthe execution phase and hence save processor performance when the sameinstruction word parts are reused.

With the increasing complexity of the processors and the demands on theprocessing speed, it becomes clear that it is necessary to achieve ahigher level of compression when coding the instruction word parts anddecoding them in order to produce the VLIW (Very Long Instruction Word),since increasing the processing speed in another way, e.g. by increasingthe operating clock frequencies, hits physical boundaries.

Consideration is now being given to ways of increasing the processorperformance during the execution phase by increasing the level ofcompression of the primary instruction words into their dividedinstruction word parts regardless of specific features (periodicity) ofthe FIWs.

SUMMARY OF THE INVENTION

In accordance with the principles of the invention, procedures areprovided for actuating function units in a processor.

An exemplary procedure has a first step involving a primary instructionword being divided, in the configuration phase, into the series of aparticular number of instruction word parts which are used forconstructing a respective VLIW during the execution phase.

In this case, a respective first and second FIW (Function InstructionWord part) is preceded with an associated first or second operatingcode. This thus determines how the cache's memory location taken up bythe respective FIW is handled in the execution phase.

In addition, the respective first or second operating code is followedby an associated first or second tag which represents the informationregarding which first or second FU actuates the respective FIW.

The first or second operating code and its associated first or secondtag are respectively combined with the respective first and second FIWsto form the first and second TVLIW containers.

In this context, all of these represent the TVLIW.

A second step involves the respective available TVLIW being convertedinto an HVLIW in the configuration phase. A general header is put infront in the HVLIW.

When converting the TVLIW into the HVLIW, the latter with thecode-compressed general header structure it contains replaces allfunctions of the TVLIW.

In one variant, the inventive object is achieved by implementing a“Command Code” mode of operation of the HVLIW and its associated generalheader. This general header stores the information, in coded form, whichindicates all combinations regarding which first and second FIW(instruction word part) is provided, after decoding, in the executionphase, for actuating a respective first and/or second FU (function unit)in the processor.

In addition, the general header stores which first and/or second FIWtakes up memory locations in the cache and whether or which operationsare to be executed with the respective memory content in the executionphase in the cache when constructing the VLIW.

The aim of this solution is for the desired compression of theinstructions to be implemented in the “Command Code” mode of operationof the HVLIW by combining a plurality of FIWs and an associatedcombination of the details regarding which of the FUs is to be actuatedby which FIW, and also which FIW takes up particular memory locations inthe cache when the VLIW is constructed and which operations are thenexecuted with the memory content of said memory locations in relation toother memory locations in the cache.

This saves memory space and conserves processor performance.

One advantageous form of the variant of the inventive manner ofachieving the object is achieved by virtue of the first part of thegeneral header being provided with a header mode which containsinformation about the “Command Code” mode of operation of the HVLIW andof the general header.

This is followed by a second part which contains the respective mostneeded combination regarding which of the respective FUs is actuated bywhich first or second FIW.

This most needed combination is dictionary as a coded table value.

A third part is connected as CE information (Cache Extra information)and contains a pointer which refers to a provided location in thedictionary.

The last part of the general header which is provided is thesupplementary information.

The general header is followed directly by the first and second FIWsneeded for constructing the VLIW.

This inventive solution lays emphasis on “Command Mode” mode ofoperation with general header which is very flexible and types of“Command Code”. This is also providing the a structured supports allintended to remain valid for further development and updates and tosafeguard its compression options.

A further variant of the inventive manner of achieving the object is fora “reference instruction” mode of operation of the general header to beimplemented in which the FIWs provided for constructing the VLIW in theexecution phase are buffer-stored generally in the cache.

In this context, the associated header mode bears a correspondinglydecodable tag for this “reference instruction” mode of operation. The“reference instruction” mode of operation is specific HVLIW.

The latter contains an address statement which is used to refer to areference instruction.

In addition, the subsequent HVLIW, which likewise bears the tag for the“reference instruction” mode of operation, contains a relative addressfor the address provided by the reference.

This has a mask appended to it which represents the FUs which are to beexcluded from the actuation.

In the case of this beneficial variant of the inventive solution, theimplementation of the specific “reference instruction” mode of operationof HVLIWs avoids the long instructions for the processor kernel, whichturn out to be long even in the “Command Code” header mode, for example,because they need to be able to be used for a large number of FUs(Function Units).

As a result, respective start and end phases of the instructions arealso required for actuating the basic constituents of the individualFUs.

On account of a large number of identical FIWs which are produced foractuating the FUs in the instructions, e.g. in digital signal processors(DSPs), it is obvious from knowledge of the instructions for theprocessor kernel that the respective start and end phases of theinstructions are redundant for the respective FUs.

This redundancy is avoided by the inventive solution by virtue of theHVLIW which initiates the “reference instruction” mode of operationbeing used to prescribe an address statement as a reference.

In the subsequent HVLIW of the “reference instruction” mode ofoperation, said HVLIW's general header is used to communicate only arelative address statement which can be used to decode the necessary FIWin the execution phase.

After the general header, this HVLIW likewise indicates the first and/orsecond FU (function unit), for which this particular instruction is notintended to be used, in coded form.

As a mask, which excludes the actuation of FUs, this statement can bemade much shorter than a statement of all FIWs which are to be actuated.

Hence, for HVLIWs, the respective start and end phases of the FIWintended for actuating the FUs provided need to be indicated only oncein the general header in the “reference instruction” mode of operation.This saves memory space.

Since this compression does not require the respective complete startand end phases of the instructions to be processed during VLIWconstruction, the processor performance in the execution phase isconsequently likewise under less of a strain as well.

One specific variant of the inventive manner of achieving the objectwhich implements the “reference instruction” general header's mode ofoperation in locally beneficial fashion is for the specific HVLIW whichinitiates the “reference instruction” mode of operation to refer, as acontained address statement, to the preceding HVLIW.

One further specific variant of the inventive manner of achieving theobject which implements the “reference instruction” general header'smode of operation in globally beneficial fashion is for the specificHVLIW which initiates the “reference instruction” mode of operation torefer, as a contained address statement, to a general address.

One advantageous extension to the manner of achieving the inventiveobject specifically for the “Command Code” mode of operation of theHVLIW is for the execution phase to involve the HVLIW being decoded in adecoder which is equipped with a header decoder, a CMDT (Command CodeDecompression Table), a cache and a cache miss repair logic unit, theHVLIW being available in buffer-stored form.

The header decoder identifies the “Command Code” mode of operation ofthe general header from the header mode stored therein.

In addition, the identified header mode is taken as a basis fordecompressing the values of the FU-C which are provided in the generalheader by means of a comparison with the CMDT and in conjunction withthe CE information which is likewise taken from the general header.

The identified header mode taken as a basis for processing thesupplementary information in the general header.

Possible incorrect access during buffer-storage in the cache (cachemiss) is remedied by the execution of an error handling routine in thecache miss repair logic unit.

Finally, the valid VLIW is provided at the output of the decoder.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features of the invention, its nature, and various advantageswill be more apparent from the following detailed description and theaccompanying drawings, wherein like reference characters represent likeelements throughout, and in which:

FIG. 1 is a schematic block diagram illustrating the steps of aprocedure for actuating function units of a processor in accordance within accordance with the principles of the present invention.

FIG. 2 is a schematic block diagram illustrating the steps of aprocedure for actuating function units of a processor in accordance within accordance with the principles of the present invention.

The following is a list of the reference numerals used in FIGS. 1 and 2:

-   -   1. TVLIW (jagged Very Long Instruction Word)    -   2. First operating code    -   3. First tag    -   4. First FIW (Function Instruction Word part)    -   5. Second operating code    -   6. Second tag Second FIW    -   7. Code analyzer    -   8. Dictionary    -   9. HVLIW (Headed Very Long Instruction Word)    -   10. First TVLIW container    -   11. Second TVLIW container    -   12. General header Header mode    -   13. FU-C information (Function Unit Combination information)    -   14. CE information (cache Extra information)    -   15. Supplementary information    -   16. Code converter    -   17. First FU (Function Unit)    -   18. Second FU (Function Unit)    -   19. Processor    -   20. VLIW (Very Long Instruction Word)    -   21. Decoder    -   22. Header decoder    -   23. CMDT (Command Code Decompression Table)    -   24. Cache    -   25. Cache miss repair logic unit

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides procedures for actuating function unitsof a processor.

An inventive procedure is described herein with reference to exemplaryFIGS. 1 and 2.

FIG. 1 shows a block overview showing the compression steps which needto be executed in the configuration phase in order to convert the TVLIW1 into the HVLIW 10 in the “Command Code” mode of operation.

FIG. 2 shows a block overview of the inventive decoder 23 that, duringthe execution phase, decompresses the compressed HVLIW 10 into the VLIW22 in the “Command Code” mode of operation and decodes it, in order toactuate the processor 21.

As can be seen in FIG. 1, in the configuration phase the starting pointfor the inventive compression is the presence of the TVLIW 1. In anexemplary embodiment this comprises the first and second TVLIWcontainers 11; 12.

The respective first or second TVLIW container 11, 12 is available withits constituents: the first or second operating code 2, 5; the first orsecond tag 3, 6; and the first or second FIW 4, 7.

In the order which arises, a respective TVLIW container is supplied to acode converter 18 and at the same time a code analyzer 8 ascertains thecombination of the three constituents of a TVLIW container in terms ofthe frequency of their occurrence in relation to the further TVLIWcontainers of the respective TVLIW by comparison with the details in adictionary 9.

These details are made available to the code converter 18. The lattercodes a general header 13 therefrom according to the mode of operationprovided and logically combines it with the respective first or secondFIW 4, 7, that are are taken from the first and second TVLIW containers11, 12, provided in succession.

When all the TVLIW containers of the TVLIW 1 have been processed thestructured general header 13 is provided and is available in the headermode 14, FU-C information 15, CE information 16 and supplementaryinformation 17 parts. The general header 13 is put in front of theseries of first and second FIWs 4, 7. A now complete HVLIW 10 is thusstored in the memory.

Subsequently, a further TVLIW 1 may be compressed.

The end of the inventive compression is reached when all of the TVLIWs 1have been converted into a respective HVLIW 10.

As can be seen in FIG. 2, in the execution phase, the use of inventivedecoder 23 for the decompressing/decoding the HVLIW 10 is triggeredafter the instructions have been buffer-stored (fetched) and hence uponprovision of the HVLIW 10 and decoding of its header mode 14 using anavailable “Command Code” mode of operation.

Subsequently, the general header 13, as a constituent of the HVLIW 10,is buffer-stored in its constituents in the cache 26 and is decodedusing the header decoder 24.

First, the first part of the general header 13, the header mode 14, isused to identify its mode of operation, and the decoder 23 is setaccordingly.

The second part of the general header 13, the FU-C information 15,provides the information for the first and second FUs 19, 20 regardingwhich of the first and second FIWs 4; 7 need to be taken into account bythe CMDT 25.

From the third part of the general header 13, the CE information, thearea of the CMDT 25 which is to be taken into account is processed. Thesupplementary information 17 is taken from the last part of the generalheader 13.

Any incorrect access to the cache 26 which may be identified is remediedby the cache miss repair logic unit 27.

This information is used to construct the VLIW 22 by arranging therespective first and/or second FIWs 4, 7 in the VLIW 22 according to thedecoded order and the position in which the first or second FU 19, 20are subsequently actuated on the processor 21.

1-7. (canceled)
 8. A method for actuating function units in a processor,wherein a configuration phase involves a series of primary instructionwords that come from a translation of a program code being divided intoa series of instruction word parts, with a program cycle involvinginstruction words which actuate the processor being constructed in thefull instruction word length to form a VLIW and being buffer-stored inan instruction word memory (cache), the method comprising: a first stepthat involves a primary instruction word being divided, in theconfiguration phase, into the series of a particular number ofinstruction word parts which are used for constructing a respective VLIWduring the execution phase, with a respective first and second FIW(Function Instruction Word part), being preceded with an associatedfirst or second operating code, which thus determines how the cache'smemory location taken up by the respective FIW is handled in theexecution phase, wherein the respective first and second operating codeare respectively followed by an associated first and second tag thatrepresent the information regarding which of the first and the second FUactuates the respective FIW, wherein the respective first and secondoperating code and their associated first or second tag are combinedwith the respective first and second FIWs to form the first and secondTVLIW containers all of which represent the TVLIW; and a second stepthat involves the respective available TVLIW being converted into anHVLIW in the configuration phase, wherein the HVLIW contains a precedinggeneral header, and wherein the HVLIW with its code-compressed structurereplaces all functions of the TVLIW.
 9. The method of claim 1 wherein aCommand Code mode of operation of the HVLIW and its associated generalheader is implemented so that the general header is followed directly bythe first and second FIWs required for constructing the VLIW (22),wherein the general header stores the information in coded form, whichindicates all combinations regarding which of the first and second FIW(instruction word part) is provided, after decoding in the executionphase for actuating a respective first and/or second FU (function unit)in the processor, and wherein the general header stores which first and/or second FIW take up memory locations in a cache and whether or whichoperations are to be executed with the respective memory content in theexecution phase in the cache when constructing the VLIW.
 10. The methodof claim 1 wherein a first part of the general header is provided with aheader mode that contains information about the “Command Code” mode ofoperation of the HVLIW and of the general header, wherein the first partis followed by a second part that stores, coded as table values, therespective most needed combination regarding which of the respective FUsis actuated by which of the first and second FIW, wherein a third partis connected as CE information and contains a pointer which refers to aprovided location in a dictionary, and wherein the last part of thegeneral header provided is the supplementary information.
 11. The methodof claim 1 wherein a “reference instruction” mode of operation of theHVLIW and of the contained general header is implemented in which theFIWs provided for constructing the VLIW in the execution phase arebuffer-stored in the cache, wherein the associated header mode bears acorrespondingly decodable tag for this “reference instruction” mode ofoperation, wherein the “reference instruction” mode of operation isinitiated by a specific HVLIW that contains an address statement whichis used to refer to a reference instruction, wherein the subsequentHVLIW which likewise bears the tag for the “reference instruction” modeof operation, contains a relative address for the address statementprovided by the reference, and wherein a mask appended to it for the FUswhich are to be excluded from the actuation.
 12. The method of claim 4wherein the address statement of the specific HVLIW which initiates the“reference instruction” mode of operation refers to a general address.13. The method of claim 1 wherein the execution phase involves the HVLIWbeing decoded in a decoder which is equipped with a header decoder, aCMDT, a cache and a cache miss repair logic unit, wherein the HVLIW isbuffer-stored in the cache, and wherein the header decoder identifiesthe mode of operation of the general header from the header mode storedtherein, wherein the identified header mode is taken as a basis fordecompressing the values of the FU-C information which are provided inthe general header by means of a comparison with the CMDT and inconjunction with the CE information which is likewise taken from thegeneral header, wherein the identified header mode is taken as a basisfor processing the supplementary information in the general header, andwherein possible incorrect access during buffer-storage in the cache(cache miss) is remedied by the execution of an error handling routinein a cache miss repair logic unit and a valid VLIW is provided at theoutput of the decoder.